1. Technical Field
The present invention relates generally to a data transmitter/receiver, and more particularly, to a rail-to-rail is comparator and a pulse amplitude modulation (PAM) receiver using the same.
2. Related Art
A multi-level input/output system is a concept designed to transmit and receive a larger amounts of data without increasing a data transmission rate. In order to support the multi-level input/output system, various modulation methods such as pulse amplitude modulation (PAM), pulse duration modulation (PDM), and pulse position modulation (PPM) may be used.
Among the modulation methods, the PAM changes only the amplitude of a pulse without changing the width and period of the pulse. According to the number of symbols M to be transmitted, the PAM may be expressed as M-PAM (M is a natural number equal to or larger than two). That is, symbols transmitted and received in an M-PAM system have any one of M levels. The PAM is used in a system for converting an analog signal into a pulse-type digital signal. The system may include a communication system between integrated circuits (ICs), a power line communication system, a high-speed digital communication system, an ultra wideband communication system, and the like.
In a communication system using the M-PAM, a receiver requires reference signals having a constant voltage level to determine the voltage levels of symbols. Desirably, the receiver may determine the levels of received symbols using (M−1) reference signals. In order for the receiver to accurately determine the levels is of received symbols, a voltage margin between M symbols may be set to a large value.
However, with an increase of M, the voltage margin between symbols inevitably decreases. Furthermore, when the system is designed for low power consumption, a high-performance device is required to restore the received symbols.
In general, the receiver of the M-PAM system may include a comparison circuit, a decoder, and an output buffer. The comparison circuit is configured to compare an input signal to a reference voltage, amplify the compared signal, and output the amplified signal as a thermometer code. The decoder is configured to convert an output signal of a differential amplifier into corresponding data. The output buffer is configured to amplify the binary signal outputted from the decoder and output the amplified signal.
When the comparison circuit is to compare the input signal to the reference signal it must be able to accurately determine the level of the input signal. A current mode logic (CML) comparator and a CMOS dynamic comparator are widely known as circuits used for the comparison circuit.
FIG. 1 illustrates an example of a conventional CML comparator.
Referring to FIG. 1, a load is formed by serial connection between an inductor and a resistor. In FIG. 1, VINP and VINM represent analog differential inputs, VRP and VRM represent differential reference voltages, and VOUTP and VOUTM represent is output voltages of the comparator. When complementary clock signals VCLKP and VCLKM are at low and high levels, respectively, cross-coupled switching elements M7 and M8 are turned off, switching elements M3 and M6 are enabled, and the comparator operates as a pre-amplifier. On the other hand, when the complementary clock signals VCLKP and VCLKM transit to high and low levels, respectively, the switching elements M7 and M8 are enabled, and the comparator operates a regenerative latch.
Cascode elements M1 and M2 serve to reduce parasitic capacitance at an output node and improve a regenerative time constant. Furthermore, the cascode elements M1 and M2 prevent noise from being introduced into the reference voltages VRP and VRM. The gate terminals of the cascode elements M1 and M2 are controlled by the clock signal VCLKM, and switching elements M9 and M10 are controlled by the same clock signal VCLKM. Since the source potential of the cascode elements M1 and M2 is higher than the source potential of the switching elements M9 and M10, the cascode elements M1 and M2 are turned on later than the switching elements M9 and M10. Therefore, residual charges from the switching elements M7 and M8 are discharged through the output node, and disturbance between the reference voltages does not occur.
In the CML comparator illustrated in FIG. 1, all amplifiers used therein operate in an active region. Furthermore, when comparing an input voltage to the reference voltage, the CML comparator consumes a current as a tail current at all time. Therefore, the power consumption thereof inevitably increases. Furthermore, since there is a limitation on the range of the input voltage and the reference voltage, it is difficult to acquire high voltage resolution in a low power supply voltage environment. FIG. 1 also illustrates switching elements M4, M5, M11, and M12, power supply voltage VDD, and VSS.
FIG. 2 illustrates an example of a CMOS dynamic comparator. FIG. 2 also illustrates switching elements M25 to M32, power supply voltage VDD, and VSS.
The comparator illustrated in FIG. 2 performs a reset/regenerative operation according to the level of a clock signal CLK, compares input signals INP and INN to reference voltages REFP and REFN, respectively, and generates output voltages OUTP and OUTN at a high or low level.
The CMOS dynamic comparator has an advantage in that it has smaller power consumption than the CML comparator. However, when the levels of the input voltages INP and INN and the reference voltages REFP and REFN are lower than the threshold voltages of amplifiers, that is, switching elements M21 to M24, the amplifiers may be turned off. In this case, the CMOS dynamic comparator cannot operate.
That is, since the input voltage range is limited, it is difficult to guarantee a normal operation in a low power supply voltage environment.